The current invention relates to a memory controller in an application specific integrated circuit (ASIC), and in particular, to a distributed memory controller scheme for controlling high speed memory devices.
A computer system relies on memory to store instructions and data that are processed by a computer system processor. In a typical computer system, the computer system processor communicates with the computer memory via a processor bus and a memory controller. Breathtaking advances have been made in both the storage capacity and speed of computer memory devices. Traditionally, the speed of memory devices has not been able to keep pace with the speed increases achieved with microprocessors and ASICs. Consequently, the speed of traditional computer systems is limited by the speed in which data and instructions can be accessed from the memory devices of the computer system.
However with the development of high speed/high bandwidth memory devices, such as provided by the memory architecture RAMBUS(copyright), the situation has changed in that it is difficult for memory controllers to make full use of the higher bandwidth made available by such high speed memory devices, particularly when a system clock speed driving these memory controllers is slower than a clock speed of the high speed memory device.
Similarly, in a system where the memory device has a wider bus interface than application logic accessing the memory device, the application logic causes a bottleneck for data flow to and from the memory device, thereby wasting precious bandwidth. A similar situation exists in the case of high speed serialised buses (such as those provided by the RAMBUS(copyright) architecture), where the memory device has a wider effective bus interface than the application logic.
A need therefore exists for a system architecture that make better use of the increased speed/bandwidth modern memory devices provide.
It is an object of the invention to substantially overcome, or at least ameliorate, one or more disadvantages of existing arrangements.
According to a further aspect of the invention, there is provided a hierarchical memory controller for allowing pseudo-simultaneous memory transactions to and from a memory device in response to memory write and memory read requests from at least one requestor module, said hierarchical memory controller comprising:
at least two arbiters for receiving and processing said memory requests; and
a controller module for controlling data flow to and from said memory device in response to signals from said at least two arbiters, said controller module being configured to operates at a frequency tat is higher than an operating frequency of said arbiters.
According to a further aspect of the invention, there is provided a method of allowing pseudo-simultaneous memory transactions to and from a memory device in response to memory write and memory read requests from at least one requestor module, said method comprising the steps of:
receiving and processing said memory requests by at least two arbiters; and
controlling data flow to and from said memory device in response to signals from said at least two arbiters by a controller module, said controller module being configured to operates at a frequency that is higher than a operating frequency of said arbiters.
According to a further aspect of the invention, there is provided a memory controller for controlling memory transactions to and from a memory device in response to memory requests from at least one requester module, said memory controller comprising:
at least one arbiter for receiving and processing said memory requests;
a controller module for controlling data flow to and from said memory device in response to signals from said at least one arbiter; and
a data dispatcher for receiving data from said controller module in response to a memory read transaction and for passing said data to said one requestor module.
According to a further aspect of the invention, there is provided a method of launching memory transactions to and from a memory in response to memory requests from at least one requester module without waiting for completion of a previous memory transaction, said method comprising the steps of:
receiving and processing said memory read requests by at least one arbiter;
controlling data flow to and from said memory device in response to signals from said at least one arbiter by a controller module;
receiving data from said controller module in response to a memory read transaction by a data dispatcher; and
passing said data to said one requester module.